Knowledge about network topology can help one select good analysis procedures for a given electrical network. The ideas involved in network topology come from a branch of geometry (topology), which is concerned with the properties of a geometrical figure that do not change when the figure is drawn in alternate forms, where those alternate forms do not involve taking apart or joining together any parts of the figure. In the case of a given electric circuit, it can be redrawn in many ways, and it still is the same circuit. So regardless of the way the circuit is drawn, it can be analyzed in the same fashion.
Much of the terminology for network topology comes from graph theory. A summary of the terms used (and their definitions) follows.
Element: a fundamental unit; e.g., in circuits a source, a resistor, a capacitor, an inductor.
Node: a point at which two or more elements are connected.
Path: A set of elements that may be traversed in order without passing through the same node twice.
Branch: a single path which connects one node to another node (via a single element).
Loop: a path where the ending node is the same as the beginning node. This is also called a closed path.
Mesh: a loop which does not contain any loops within it.
Graph: a representation of a circuit where each branch is denoted by a line segment.
Tree (of a graph): a set of branches (each denoted by a line segment) that connects every node to every other node via some path without forming a loop.
Tree branch: a branch of a graph that is part of a particular tree.
Cotree: those branches of a graph which are not part of a particular tree. This is also known as the complement of the tree.
Link: a branch of a cotree.
Cut set: a minimum set of branches that, when cut, will divide a graph into two separate parts.
Fundamental cut set: a cut set containing only a single tree branch.
Fundamental loop: A loop that results when a link is put into the tree.
There is only one graph for a circuit (although there may be many ways to draw it). Usually, there are several trees for a graph, and each tree has a corresponding cotree. As an example, consider the following circuit.
One way to draw this circuit's graph is given below.
Another graph which represents this same circuit is shown below. Note that the shape can vary significantly (just as the schematic of a circuit can be drawn in several ways), but to be a correct representation of the circuit the graph must have the same number of nodes connected in the same way.
Two of the possible trees for this graph (and their corresponding cotrees) are shown below, where tree branches are shown with solid lines and links (branches in the cotree) with broken lines. Note that in both of these example trees that there is a path from every node to every other node via some number of tree branches, yet there are no loops. Any branch of the original circuit which would cause a loop to be formed is made into a link (a branch in the cotree).
A relationship among the basic parameters of a graph that represents a circuit can be obtained. Define the following parameters:
B = number of branches in the graph
N = number of nodes in the graph
L = number of links
How many tree branches are there? A tree can be constructed by starting with one of the nodes of the original circuit and then by adding branches one by one until the tree is complete. The first branch will connect two nodes. By adding the branches after that so that one end of the new branch touches a node that is already has at least one branch connected to it and the other end of the new branch touches a node that has no branches connected to it allows one to continue to build a tree and to reduce the number of unconnected nodes by one. When the tree is complete, there will be one less branch than there are nodes, thus a tree contains N - 1 branches. Since the entire graph has B branches, the number of links can be determined from the equation
L = B - (N - 1) = B - N + 1
A cut set divides a graph into two independent parts. In terms of the original circuit, a KCL equation can be written for either part of the circuit divided by the cut; such a KCL equation is called a cut-set equation. Two cut sets for the example graph are shown below. Note that each cut set divides the graph (which represents a circuit) into two parts.
A cut set that cuts through only a single tree branch is called a fundamental cut set. Two fundamental cut sets for one of the trees of the example graph are shown below, one as a broken red ellipse and one as a broken blue ellipse. (This example has two additional fundamental cut sets which have not been marked on the figure.)
The dual of a fundamental cut set is a fundamental loop. Each time a link is inserted into a tree as a potential tree branch, a loop is formed in the tree (thus the resulting object is no longer a tree). Such a loop is called a fundamental loop. One such loop is shown below for one of the example trees. The broken red line shows the loop that results when the link on the left edge of the tree is changed to a branch (as shown by the blue line).
The ideas presented above about circuit topology can be used to find the best way to analyze a circuit. Similar to the commonly-used methods (nodal analysis and mesh analysis), these methods are also based upon Kirchhoff's Laws. Tree-branch analysis uses KCL (Kirchhoff's Current Law) but no reference node is selected like is done in nodal analysis; all KCL equations are written in terms of tree branch voltages instead of node voltages.
Loop analysis uses KVL (Kirchhoff's Voltage Law) but the loops chosen may not necessarily be meshes. Instead, each loop needs to be a fundamental loop obtained by inserting a link into a tree. The details for these procedures are given below. Notice that for both of these procedures, steps 1 and 2 are identical. These two steps give you a tree, from which it then becomes possible to determine which analysis method would give you the fewest Kirchhoff's equations.
Note that the number of KCL equations that need to be written is equal to the number of tree branches minus the number of voltage sources.
(To the Beginning of General Nodal Analysis Method)
Let's apply the above General Nodal Analysis method to the example circuit given earlier. Using the process to grow a tree, the two voltage sources must be in the tree and the controlling current for the current-controlled voltage source must be in the cotree. One possible tree for this circuit (and its corresponding cotree) is shown below.
Now label the tree branches. Two of the tree branches are the voltage sources in the circuit (20V and 40Ix), so these labels should be used on the tree branches that represent them. The other two tree branches for this network did not have voltages labeled in the original circuit. So we select meaningful names like V4 for the voltage across the 4 Ω resistor and V10 for the voltage across the 10 Ω resistor. The labeled tree that results (and its corresponding cotree) is shown below. Note that not only is it necessary to give names to the voltages across the 4 Ω and 10 Ω resistors, polarities for those voltages must be assigned. Notice also that voltages on the links are not labeled.
Locate and label each fundamental cut set. This circuit has four branches in the tree, so there are four fundamental cut sets. The following figure shows these fundamental cut sets (labeled as FCS #1, FCS #2, FCS #3, and FCS #4).
KCL equations need to be written at each fundamental cut set that does not cut a voltage source. For the example circuit, FCS #2 and FCS #4 each cut a voltage source (the dependent voltage source and the 20V independent source, respectively), so KCL equations do not need to be written for those fundamental cut sets.
FCS #1 cuts the 4W and
6 Ω resistors, so you need
equations for the currents flowing in those two resistors.
By Ohm's Law the current leaving the cut and flowing
through the 4 Ω resistor
is V4 / 4. Obtaining an equation for the current
leaving the cut and
flowing through the 6 Ω resistor
is more challenging, since that resistor is not in the tree.
(To properly solve the equations you write, it is necessary
that all voltages in the equations be voltage values found in the
tree.) Examining
the circuit you find that the voltage across the
6 Ω resistor is V4
- 40Ix + V10. (You can verify
this equation by writing KVL around the loop that results
from placing the link that represents the
6 Ω resistor in the tree.)
The current in the 6 Ω resistor
is this voltage divided by 6, or
(V4
- 40Ix + V10) / 6. Therefore the
KCL equation at FCS#1 is (the currents leaving the FCS area):
V4 / 4 + ( V4
- 40Ix + V10 ) / 6 = 0.
Similarly, you need to write the KCL equation at FCS#3 for the currents
leaving that area. The current leaving the area through the
6 Ω resistor is the voltage across
that resistor divided by the resistance, in this case
( -V10 + 40Ix - V4 ) / 6.
The current leaving the cut set through the 10 Ω
resistor is -V10 / 10. Finally the current leaving FCS#3
through the 5 Ω resistor is
( -20 - V10 + 40Ix ) / 5.
Summing these up gives the KCL equation for FCS#3:
( -V10 + 40Ix - V4 ) / 6 +
( -V10 ) / 10 +
( -20 - V10 + 40Ix ) / 5 = 0.
The dependency in this circuit is on a current. This current needs to be written in terms of tree branch voltages via the appropriate Ohm's Law equation. The dependent current Ix is the current flowing through the 5 Ω resistor from top to bottom. The voltage across this resistor (in terms of tree branch voltages) is -20 - V10 + 40Ix, so Ix = ( -20 - V10 + 40Ix ) / 5. Solving for Ix gives Ix = ( V10 ) / 35 + 4 / 7.
Substituting the equation for Ix back into the two FCS equations gives you two equations with two unknown tree branch voltages (V10 and V4). Solving for these unknown tree branch voltages gives V10 = 50V and V4 = 12V. Knowing the values of these two tree branch voltages allows you to solve for any other value in the circuit.
(To the Beginning of General Nodal Analysis Example)
Note that the number of KVL equations that need to be written is equal to the number of links minus the number of current sources.
To the Beginning of Loop Analysis Method
Let's apply the above Loop Analysis method to the example circuit given earlier. Using the process to grow a tree, the two voltage sources must be in the tree and the controlling current for the current-controlled voltage source must be in the cotree. One possible tree that satisfies this requirement is shown below. (Note that other trees could be used. That would cause other link currents to be used and would yield different KVL equations than those shown below for this tree.)
Currents need to be defined for each link. The current through the 5 Ω resistor is defined in the original circuit as Ix (the controlling current for the dependent voltage source), so that name and direction should be used. On the other hand, no name or direction are given for the current flowing through the 6 Ω resistor in the original circuit, so you are free to select a name and direction for this current. Here the name I6 flowing from right to left has been chosen. Thus the labeled cotree that results is given below (along with the original tree that was used to form this cotree).
Locate and label each fundamental loop. There are two links so there are two fundamental loops. Replacing the link that has current Ix flowing in it with its corresponding branch gives fundamental loop Ix in the right side of the circuit. Replacing the link that has current I6 in it with its corresponding branch gives fundamental loop I6 that involves the outside edges of the circuit. These are shown in the following figure.
A KVL equation needs to be written for each fundamental loop that is not a loop caused by a current source. Since there are no current sources in this example, two KVL equations need to be written. Ohm's Law is used to provide voltage values for branches in a loop that contain a resistor; the currents used need to be all the loop currents that flow through the given resistor.
For the Ix fundamental loop, the KVL
equation is:
5Ix + ( -40Ix ) + 10( Ix
+ I6 ) + 20 = 0.
For the I6 fundamental loop, the
KVL equation is:
6I6 + 4I6 + ( -40Ix )
+ 10( I6 + Ix ) = 0.
There are no voltage-controlled dependent sources in this circuit, so there is no need to write any further equations. The two KVL equations written in this case involve just two unknown values, so they can be solved by standard algebraic methods. The results are Ix = 2A and I6 = 3A.
With the knowledge of the values of loop currents Ix and I6 it is possible to determine any other value desired for this circuit. For example, the branch current flowing from right to left in the 10 Ω resistor is I6 + Ix = 3 + 2 = 5A; the voltage across the 4 Ω resistor (plus on top) is I6×R4 = 3×4 = 12V; the power produced by the independent voltage source is - V20×Ix = - 20×2 = -40W generated; and so on.
(To the Beginning of Loop Analysis Example)
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