Assistant Professor
Department of Electrical and Computer Engineering
North Dakota State University

• ECE 376: Embedded Systems, Fall 2011
• ECE 374: Computer Organization, Spring 2009, Spring 2010
• ECE 373: Assembly Programming, Spring 2009, Spring 2010
• ECE 375: Digital System Design and Implementation, Fall 2008, Fall 2009
• ECE 796: Computer-Aided Verification, Spring 2008, Fall 2009

• Sudarshan K. Srinivasan and Raj S. Katti: Desynchronization: Design For Verification, Formal Methods in Computer Aided Design (FMCAD) , 2011.

• Sudarshan K. Srinivasan, Yangwei Cai, and Koushik Sarker: Refinement-Based Verification of Elastic Pipelined Systems, Accepted to appear: IET Computers & Digital Techniques .

• Rajesh Kavasseri and Sudarshan K. Srinivasan: Joint Placement of Phasor and Power Flow Measurements for Observability of Power Systems, Accepted to appear: IEEE Transactions on Power Systems .

• Rajesh Kavasseri and Sudarshan K. Srinivasan: Joint Placement of Phasor and Conventional Power Flow Measurements for Fault Observability of Power Systems, Accepted to appear: IET Generation, Transmission & Distribution .

• Sudarshan K. Srinivasan: Automatic Refinement Checking of Pipelines with Out-of-Order Execution. IEEE Transactions on Computers , 2010.

• Sudarshan K. Srinivasan: Optimization Techniques for Verification of Out-of-Order Execution Machines , Journal of Electrical and Computer Engineering , vol. 2010,

• Panagiotis Manolios and Sudarshan K. Srinivasan: Verifying Pipelines with BAT. Design and Verification of Microprocessor Systems for High-Assurance Applications, edited by David S. Hardin. Springer, March 2010.

• Raj S. Katti and Sudarshan K. Srinivasan: Sub-Optimal Data Compression and the Subset Sum Problem. International Journal of Electronics and Communications , 2010.

• Rajesh G. Kavasseri and Sudarshan K. Srinivasan: Joint Optimal Placement of PMU and Conventional Measurements in Power Systems IEEE International Symposium on Circuits and Systems}, 2010.

• Raj S. Katti, Sudarshan K. Srinivasan and Aida Vosoughi: Proving Eavesdropper Insecurity of Randomized Arithmetic Codes IEEE Transactions on Information Forensics and Security, accepted to appear.

• Sudarshan K. Srinivasan, Koushik Sarker, and Raj S. Katti: Verification of Synchronous Elastic Processors. IEEE Embedded Systems Letters 1(1): pages: 14-18 (2009).

• Sudarshan K. Srinivasan, Koushik Sarker, and Raj S. Katti: Token-Aware Completion Functions for Elastic Processor Verification. Journal of Electrical and Computer Engineering, (2009).

• Sudarshan K. Srinivasan and Raj S. Katti: Verification of Desynchronized Circuits. IEEE International Symposium on Circuits and Systems (ISCAS'09).

• Raj S. Katti and Sudarshan K. Srinivasan: Efficient Hardware Implementation of a new Pseudo-random Bit Sequence Generator IEEE International Symposium on Circuits and Systems (ISCAS'09).

• Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic verification of safety and liveness for pipelined machines using WEB refinement. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)

• Panagiotis Manolios, Sudarshan K. Srinivasan: A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. IEEE Trans. VLSI Syst. 16(4): 353-364 (2008)

• Panagiotis Manolios, Sudarshan Srinivasan, and Daron Vroon. BAT: The Bit-Level Analysis Tool. Nineteenth International on Computer Aided Verification (CAV'07), 2007.

• Panagiotis Manolios, Sudarshan K. Srinivasan, and Daron Vroon. Automatic Memory Reductions for RTL-Level Verification. ACM-IEEE International Conference on Computer Aided Design (ICCAD'06), 2006

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. Journal of Automated Reasoning, 37(1-2): 93-116 (2006)

• Roma Kane, Panagiotis Manolios, and Sudarshan K. Srinivasan. Monolithic Verification of Deep Pipelines with Collapsed Flushing. ACM-IEEE Design, Automation, and Test in Europe (DATE'06) , 2006

• Panagiotis Manolios and Sudarshan K. Srinivasan. Verification of Executable Pipelined Machines with Bit-Level Interfaces. ACM-IEEE International Conference on Computer Aided Design (ICCAD'05) , November 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Complete Compositional Reasoning Framework for the Efficient Verification of Pipelined Machines. ACM-IEEE International Conference on Computer Aided Design (ICCAD'05) , November 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Computationally Efficient Method Based on Commitment Refinement Maps for Verifying Pipelined Machines. ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'05), 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. 13th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME'05), 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. Design Automation and Test in Europe (DATE'05), 2005.

• Panagiotis Manolios and Sudarshan K. Srinivasan. A Suite of Hard ACL2 Theorems Arising in Refinement-Based Processor Verification. ACL2 Workshop (ACL2'04), 2004.

• Panagiotis Manolios and Sudarshan K. Srinivasan. Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements. Design Automation and Test in Europe (DATE'04), 2004.

• Jun Cheol Park, Vincent J. Mooney, Sudarshan K. Srinivasan. Combining Data Remapping and Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems. Microelectronics Journal 34(11): 1019-1024 (2003).

• Sudarshan K. Srinivasan, and Miroslav N. Velev Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Imprecise Data-Memory Exceptions. Formal Methods and Models for Codesign (MEMOCODE'03), 2003.

• Panagiotis Manolios and Sudarshan K. Srinivasan. Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements. CERCS TR# GIT-CERCS-03-17,, 2003.

• Sudarshan K. Srinivasan, Jun Cheol Park, and Vincent J. Mooney. Combining Data Remapping and Voltage/Frequency Scaling of Second Level Memory for Energy Reduction in Embedded Systems. Embedded System Codesign (ESCODES'02) , 2002.